Some great analysis on SSD wear leveling and power consumption

Some great analysis by Cullen Logan at Amazon.com appeared on LinkedIn over the weekend in response to my post “Are Enterprise SSDs a “bad” idea? Four tips and counter-tips for your consideration”:

“To put some raw data out there, consider a single 8Gb MLC NAND with 4096 blocks. If a naive approach were taken that performs an ERASE/REPROGRAM every minute, the typical 10,000 cycle limit would be reached in just 7 days (60 x 24 x 7 = 10,080 = good-bye block).

But as Steve points out there are really smart people working on this stuff. Using a perfect wear-leveling scenario that evenly distributes ERASE/REPROGRAM cycles across all 4096 blocks would result in each block being written a maximum of 3 times in that 7 day period 10,080/4096 = ~2.46. Put another way, wear leveling can extend the life of the MLC NAND to over 77 years using this simplistic example.

(10,000 x 4096)/(60×24) = 28,444 days = ~77.87 years

Other topics that should be considered is whether or not the controller utilizes partial page writes (which increases read disturbances), background operations, and many other features defined in JEDEC specs for eMMC – although eMMC is not exactly the same as SSD; they share many things in common.

While some anecdotal comments in this thread suggest that power is not something to consider with SSDs, I tend to disagree. As bus frequencies increase we must compensate by attempting to lower the voltage supplied, to help the overall power equation. In that equation voltage is squared, so any reduction in voltage is a big win. Lowering the voltage on HDDs is a larger hurdle due to mechanical parts, while wafer processing tends to lean in favor for SSDs and required voltage.

I could probably write for another hour about this, but my meta-point is that SSDs are in no way bad. As Steve mentioned ECC selection will need to evolve or perhaps become application dependent, which will result in extra bits per block, but will provide the right ECC for an application’s target BER.

My only complaint is the lack of transparency in the methods used by controller vendors in how exactly they manage bad blocks. It makes robust testing nearly impossible if not done in an oven, and even then you can’t get raw data on block failures, because the controller takes care of it by design and how it does so is secret sauce for the controller vendor.

SSDs are here to stay. Any enterprising company will have backup measures in place already for critical and perhaps non-critical data, so price will probably be a large determining factor for large-scale corporate purchases. Just my $0.02.

Thanks Steve for a great post to generate some activity.”

Posted by Cullen Logan.

Thanks, Cullen!

Add OCZ to the growing list of SSD vendors differentiating their drives with a proprietory controller

SSD vendor OCZ has been showing its new top-of-the-line Vector 2.5-inch SSD at this week’s Intel Developers Forum in San Francisco. During a conference call with analysts, OCZ CEO Ryan Peterson reportedly discussed the controller in the new SSD. It’s the Indilinx Barefoot 3, an all-new design internally developed by OCZ, which bought controller vendor Indilinx last year.

Many SSD vendors have been acquiring SSD controller vendors or developing in-house SSD controllers as a way to differentiate their storage products.

For more discussion of this topic, see:

Using SSD controller technology as a differentiator: Kingston adds another data point with SSDNow Enterprise-class drives

Need yet another argument for designing your own SSD controller?

Add Hitachi Data Systems to the growing list of companies developing their own SSD controllers

How Skyera developed the 44Tbyte, enterprise-class Skyhawk SSD from the ground up. A System Realization story.

More on developing your own SSD controller chip. Is rolling your own right for you?

STEC’s MACH16 Slim 2.5-in SATA SSD requires small footprint, fits in small embedded spaces

Micron introduces Enterprise-class, 2.5-inch SSD with PCIe interface

Examining The SSD Industry – Researching The Controller or Processor

IDT announces DDR4 register chip for DDR4 registered DDIMMs and 3D die stacks

IDT has announced a small but essential component for the development of advanced DDR4 DIMMs: the 4RCD0124 DDR4 register. A device of this type is required for building DDR4 DIMMs to provide registered buffering. In addition, the 4RCD0124 DDR4 register includes advanced RAS (reliability, availability, and serviceability) features and support for 3D SDRAM die stacking on the DIMM.

Will The Apple iPhone 5 Use PCM?

An investment site called Seeking Alpha has published a bit of strange forensic research that leads it to claim that the Apple iPhone 5 that will be announced tomorrow employs phase-change memory (PCM). What clue led to this conclusion? It was the mention of PCM in a US patent application filed early last year on January 14, 2011, number 20120185797.

Part of the patent application’s description reads:

“[0023] The data processing system 100 includes memory 110 which is coupled to the microprocessor(s) 105. The memory 110 may be used for storing data, metadata, and programs for execution by the microprocessor(s) 105. The memory 110 may include one or more of volatile and non-volatile memories, such as Random Access Memory (“RAM”), Read Only Memory (“ROM”), Flash, Phase Change Memory (“PCM”), or other types of data storage.”

Now this is a real stretch of the imagination if you know how all inclusive companies try to make patent applications. Nevertheless, Micron recently introduced a combo SDRAM/PCM product—see “3D Thursday: Micron stacks Phase-Change Memory and SDRAM”—although the amount of PCM in that product isn’t enough to hold an iPhone’s operating system.

So could the new Apple iPhone 5 contain PCM? It’s certainly not impossible. I guess we just have to wait until tomorrow to find out.

Western Digital Sampling 5mm, 2.5 inch, 500 Gbyte hybrid HDD with NAND Flash

Western Digital just started shipping 7mm, 2.5-inch HDDs earlier this year and has now announced that it is sampling a 5mm, 2.5-inch, 500Gbyte hybrid HDD with integrated NAND Flash caching. The drive will be showcased during Western Digital’s Investor Day on September 13. The announcement quotes spokespeople from both Acer and Asus, two of the leading PC notebook vendors that appear to be collaborating with Western Digital on the slimmer drive, which is clearly targeted at Ultrabook designs. As the announcement points out, the 5mm drive consumes a little more than half of the volume of a 9.5mm drive, which is important for Ultrabooks because of the small form factor.

IBM gets patent for hi-temp PCM – (phase-change-memory) structure

Tom’s Hardware is reporting that IBM recently obtained a patent on specially formulated phase-change memory (PCM) that will operate above 150°C. This is a significant achievement because PCM has a problem with ambient thermal annealing. If the chip temperature goes too high, then the phase-change memory cells will start to self erase as they change from their amorphous state to a crystalline state. This was not a problem for the recently announced LPDDR2 PCM/SDRAM combo device from Micron. (See “3D Thursday: Micron stacks Phase-Change Memory and SDRAM”) I know it’s not a problem for the device’s 0-85°C temperature range because I asked about that problem. Operating at more than 150°C is yet another story entirely.