Denali Memory Report:
The Denali Memory Report is produced by Cadence Design Systems, Inc. It delivers memory market news, discussions of market trends, products and product strategies of the memory vendors, plus information about alliances and industry consortia.
- Some great analysis on SSD wear leveling and power consumption
- The Economist covers PCM – must be something real
- Add OCZ to the growing list of SSD vendors differentiating their drives with a proprietary controller
- IDT announces DDR4 register chip for DDR4 registered DIMMs and 3D die stacks
- Western Digital sampling 5mm, 2.5-inch, 500Gbyte hybrid HDD with NAND Flash
What's hot on the Denali Memory Report?
- Compact Flash
- Hybrid Memory Cube
- NVM Express
- Wide I/O
Category Archives: DDR
Cadence has just completed testing of its DDR4 SDRAM controller and PHY in two of the TSMC 28nm process technologies: 28HPM and 28HP. The DDR4 PHY exceeds the data rates needed to operate DDR-2400 SDRAMs and it is interoperable with … Continue reading
What does Intel’s choice of GDDR5 graphics DRAM for main memory with its Manycore Xeon Phi coprocessor say about SoC design?
George Chrysos discussed the Intel MIC (Many Integrated Core) architecture of the Knights Bridge chip (officially called the Intel Xeon Phi coprocessor) at today’s Hot Chips 24 conference and disclosed that it uses GDDR5 graphics memory as the main memory … Continue reading
Agilent has just announced a compliance test application for DDR4 SDRAM system designs. The $4500 Agilent N6462A DDR4 test application accelerates bring-up and debugging of DDR4 SDRAM-based systems by automating a bevy of physical-layer I/O testing with the company’s 9000 … Continue reading
See the future of DRAM usage, at least until 2015. Marc Greenberg from Cadence lays it out in a video
This year at DAC, Marc Greenberg gave a presentation on the near- and medium-term future of DRAM in the ChipEstimate booth. Two separate technology paths will dominate: the PC/server space and the mobile space. By 2015, PCs and servers will … Continue reading
Want more details about the new Micron 1Gbit Phase-Change Memory / 512Mbit SDRAM device? Here are several
Yesterday, Micron announced volume production of a new memory device containing one 1Gbit PCM (phase-change memory) die and one 512Mbit LPDDR2 SDRAM die. This morning, I had a conversation about this new device with Philippe Berge—Senior Director of the NOR, … Continue reading
Michael Feldman over at HPCwire.com has just published his own analysis of the Hybrid Memory Cube (HMC), which I’ve covered extensively in the EDA360 Insider and the Denali Memory Report (see below). Feldman reiterates many of the same points I’ve … Continue reading
I’ve been meaning to write about a comment regarding NAND Flash memory and SSDs written by Thomas McCormick in LinkedIn’s Solid State Storage Group and this seems like the perfect time. McCormick is an Integrated Hardware/Software Product Development Leader at … Continue reading
Earlier this month, JEDEC published the LPDDR3 specification for the next generation of low-power SDRAM that will be used in mobile devices such as smartphones, tablets, ultra-thin notebooks and similar connected devices on the newest, high-speed 4G networks. The LPDDR3 … Continue reading
“There’s no real difference between PCs and mobile phones today,” said Matti Floman from Nokia who gave the first keynote speech at last week’s JEDEC Mobile Forum. There is no difference in the types of applications run; there’s no difference … Continue reading
Multicore SoC and processor designs were our solution to the death of Dennard Scaling when IC process geometries dropped below 90nm, when processor speeds hit 3GHz, and when processor power consumption went off the charts. Since 2004, we’ve transformed Moore’s … Continue reading
Cadence Product Marketing Director Marc Greenberg—one of the speakers at last week’s EDPS conference held in Monterey, California—spoke about why the Wide I/O SDRAM is probably the “killer app” that unleashes 3D IC assembly into the mainstream. Richard Goering has … Continue reading
Free Webinar on essential memory and storage verification IP: DDR3/4, LRDIMM, 12Gbps SAS, NVMe, Ethernet. April 10.
Verification IP (VIP) is an essential component of the development process for all ICs and systems and now you have the chance to listen to a free April 10 Webinar on applying that essential component in memory and storage applications. … Continue reading
Marc Greenberg, Director of Product Marketing in the Cadence SoC Realization Design IP Group, just sent me some slides in connection with the recent introduction of the Cadence design and verification IP portfolio for LPDDR3 low-power SDRAM. I’ve already written … Continue reading
Upgrading your mobile or low-power SoC to LPDDR3? Got the right IP? You’ll need it to get maximum performance at minimum power
LPDDR3 is JEDEC’s next click on the low-power LPDDR SDRAM standard for mobile, portable, and other low-power devices. According to the JEDEC Web site, the LPDDR3 standard is still in development but the technical specs of the early devices announced … Continue reading
Want to avoid losing more than half of your SDRAM’s bandwidth? The right SDRAM controller configuration can help prevent the loss. Just ask Vivante.
Graphics processors (GPUs) suck bits out of SDRAMs the way vampires do what comes naturally to them in the immensely popular Twilight book series by Stephenie Meyer. In other words, GPUs need all the memory bandwidth they can get and … Continue reading